1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device comprising memory cells having a stacked-type capacitor comprising a cylindrical electrode.
2. Description of the Related Art
The most widely employed capacitor structure for present day DRAMs is a stacked-type capacitor structure. A stacked-type capacitor having a cylindrical storage electrode for enlarging the surface area with the effects of increasing the charge per unit area of projective plane is known in the art. The manufacturing process sequence of a conventional example of such structure is described below.
Referring to FIG. 13a, on a surface of a p-type silicon substrate 5, field oxide film 1 is selectively formed to isolate an active area. In this area, gate oxide film 2 is formed, on which polysilicon film is deposited and patterned to form a word line 3 serving also as a gate electrode. Using word line 3 and the field oxide film as a mask, ion implantation is carried out to form a pair of n.sup.+ regions 4-1 and 4-2 each on opposite sides, respectively, of word line 3. Interlayer insulating film 6-1 is deposited and a contact hole 7-1 leading to one n.sup.+ region 4-1 is opened. After bit line 15 is formed, interlayer insulating film 6-2 is deposited and another contact hole 7-2 leading to the other n.sup.+ region 4-2 is opened.
As shown in FIG. 13b, polysilicon film 11 serving as a support for a cylindrical electrode, followed by silicon dioxide film 16 serving as a core are deposited by a chemical vapor deposition (CVD) technique. As shown in FIG. 13c, after forming a core 16a of silicon dioxide film by photolithography above n.sup.+ region 4-2 (alternatively, both silicon oxide film 16 and polysilicon film 11 serving as a support are patterned at this process step), polysilicon film 13 is deposited by CVD.
As shown in FIG. 13d, anisotropic etching is applied to the entire surface of the substrate to remove polysilicon film 13 and 11 except portions at just under and on the sides of core 16a. Thus, a bottom electrode 11a and cylindrical electrode 13a are formed. Next, as shown in FIG. 13e, core 16a of silicon dioxide film is removed with buffered fluoric acid, leaving a completed lower electrode comprising electrodes 11a and 13a and connected to n.sup.+ region 4-2. Then, as illustrated in FIG. 13f, a silicon dioxide dielectric film 17 and an upper electrode 18 of polysilicon film are formed.
The fact should be noted with regard to this fabrication process that a formation of a core involves a cylindrical electrode of polysilicon film. Also, various mask patterns including those for the contact hole and the core for forming the memory cell are used as desired for fabrication of a semiconductor memory device, for checking finished quality, or for patterning parts of circuit elements.
The first of the required patterns is an alignment mark used in the photolithography process for the core pattern to be aligned with the contact pattern. A vernier pattern is commonly used as the alignment mark. For example, to attain finer checking under an optical microscope at about 1000-magnification, as shown in FIG. 14, holes 7a (recesses formed in the field area of a chip 100 simultaneously with contact hole 7-2) are used as a vernier pattern, and cores of 3 .mu.m wide and 20 .mu.m long (polysilicon films 16b and 11b formed using the cores are shown) are arranged at a position offset from holes 7a 5 .mu.m in the direction of the length. The second pattern is for evaluating, by the remaining thickness of the insulating film of silicon dioxide, whether an etch amount for forming contact hole 7-2 has been proper. This is merely a monitor contact hole 7c for detecting any under etching in the area on the substrate except for the field-oxide-film area, and another monitor hole 7b for detecting overetching on the field-oxide-film area. The size of monitor hole 7b and monitor contact hole 7c is set to about 50 .mu.m square, taking the light beam diameter and vibration under practical circumstances into consideration so as not to make difficult the positional setting of an instrument for determining the thickness of the insulating film from the reflectance spectra. Another highly required pattern is a test element group (TEG) pattern of the stacked-type capacitor, which serves for permitting the measurement, at completion, of the thickness of the dielectric film between the stacked electrode (lower electrode) and upper electrode and the height of the cylindrical electrode, these being factors deciding the storage capacitance of the capacitor.
As illustrated in FIG. 15, this TEG includes a n.sup.+ region 14 formed in the area isolated by field oxide film 1. After forming the aforesaid interlayer-insulating film 6-2 is formed in sequence contact hole 7d, bottom electrode 11b, cylindrical electrode 13b, dielectric film 17, upper electrode 18a, insulating film (not shown) and a pair of contact holes 20 one of which is connected to upper electrode 18a. Also a pair of measurement electrodes are formed at the same time as a bonding pad. Typically for the purpose of reducing the influence of noise and improving the precision of measurement, patterns having a size of about 100 .mu.m (the size of upper electrode 18a) are used. The second is a TEG used for measurement of the sheet resistance of the capacitor electrode, which as shown in FIG. 16, includes bottom electrode 11c made of polysilicon film connected to n.sup.+ region 14 through contact hole 7e and cylindrical electrode 13c are formed on the interlayer insulating film 6-2. Like the TEG shown in FIG. 15, a pair of electrode 21 connected to n.sup.+ region 14 through contact holes 20 are built, which makes it possible to measure a sheet resistance value of the capacitor electrode. The capacitor electrode, if too narrow, would affect the dimensions for the photolithography, resulting in incorrect sheet resistance measurement. Therefore, a strip geometry of unaffected dimensions, typically 10 .mu.m wide and 100 .mu.m long is used. The third another TEG (not shown) having a structure similar to cell array and modified is used for monitoring the charge of the capacitor electrode of the memory cell and the contact resistances of the contacts.
Finally, there are subsidiary patterns for making masks and character codes for identification of masks. As shown in FIG. 17, character-shaped holes 7f and 7g representing characters 1 and 2 may be opened at the same time with the contact hole 7-1. It may be permitted to form a character-shaped hole representing a digit such as 3 at the same time with contact hole 7-2, cylindrical electrode pattern 16c and bottom electrode pattern 11d. Other various patterns may be used in future.
These patterns are in many cases formed of larger holes and cores than the memory cell area. In fact, this makes it impossible to form the patterns as desired. Assuming that they are formed as intended, how the patterns change with the fabrication steps (FIGS. 13a to 13e) of the memory cell is illustrated in FIGS. 18a, 18b and 18c through FIGS. 22a, 22b and 22c with respect to three patterns: monitor hole 7b, monitor contact hole 7c, and TEG of the capacitor. Characters a, b and c attached to the figure numbers designate the cross sections taken along lines .alpha.1-.alpha.2 of FIG. 15, .beta.1-.beta.2 of FIG. 14 and .gamma.1-.gamma.2 of FIG. 14, respectively. Reference character 6 designates the combination of interlayer insulating films 6-1 and 6-2.
As shown in FIG. 13a and FIGS. 18a, 18b and 18c, holes 7-2, 7d, 7c and 7b are formed in the memory cell area, the TEG area, the monitor contact hole area on the substrate and the monitor hole area on the field oxide film, respectively. Next, as shown in FIG. 13b and FIGS. 19a, 19b and 19c, polysilicon film 11 and silicon oxide film 16 are deposited over the entire surface. Next, as shown in FIG. 13c and FIGS. 20a, 20b and 20c, cores 16a and 16d are formed in the memory cell area and the TEG area, respectively, in this step unwanted cores 16e, 16f are formed also on sides of the monitor hole and contact hole, respectively. Polysilicon film 13 is deposited, and then, as illustrated in FIG. 13d and FIGS. 21a, 21b and 21c, cylindrical electrodes 13a, 13e, 13f and 13g are formed on the sides of cores 16a, 16d, 16e and 16f, accompanied by formation of cylindrical electrode 13d also on the inside steps of core 16d. Further in the memory-cell area) as illustrated in FIG. 23, a core 19 provided with a center recess is formed under some circumstances in contact hole 7-2, to the thickness of silicon oxide film 16 during a fabrication process. In this recess, if the etch back is insufficient, cylindrical electrode or wall 13.alpha. is formed. In addition, at the portion of the cores 16e, 13f, polysilicon films 11f and 11g are left. Next, as shown in FIG. 13e and FIGS. 22a, the cores are removed, which causes cylindrical electrodes 13d (and 13.alpha. of FIG. 23) to lose mechanical support and drift.
The conventional semiconductor memory device described above has the following drawbacks.
First: in the area where a core covering contact hole exists, such as the memory cell area or the TEG area, if a step with the wall substantially perpendicular to the inside of the contact hole is formed or a recess is formed in the core, an unnecessary cylindrical electrode (13d and 13.alpha.) is formed as a result of the etch back for forming the desired cylindrical electrode. These are not formed on the lower electrode 11 of polysilicon film, and hence, after removing the core, these elements lose support and drift out. In the memory cell area, this defect can be solved negligibly by adequately selecting dimensions of the contact hole, the fabricating process of interlayer insulating film, or the core thickness. However, such means cannot solve the problem associated with the TEG area. PA1 Second: partial break-off happens occasionally to the cylindrical electrode after the core has been removed, as shown in FIG. 24. It is supposed that a cylindrical electrode, if made to be too thin, tall, or long in one sense, may happen to give way or come off totally under a perpendicular force applied to the surface of the cylindrical electrode due to water, vibration, or thermal stress during the fabrication process. If the capacitor electrode is large, this phenomenon can occur in the memory cell area as well, and in the TEG area. PA1 Third: polysilicon films 11f (to which 13f is deposited) and 11g (to which 13g is deposited) are formed on the sides of holes to avoid formation of a core therein like the monitor hole or the monitor contact hole. These unwanted polysilicon films come off after the core is removed. This is probably due to the difference in thermal expansion coefficient between polysilicon film and silicon dioxide film and thermal-mechanical impact. PA1 Fourth: when a pattern representing characters such as digits is formed with bottom electrodes and a cylindrical electrode after forming cores in an area without any hole such as a contact hole, the cores must be wet-etched away accompanied by side etching of the interlayer insulating film under the bottom electrode which then becomes unsupported and drifts out as useless substance.
As described above, the conventional semiconductor memory device offers problem associated with waste of cylindrical electrode material such as polysilicon film produced when the cylindrical electrode for the capacitor is made in the memory cell area, leading to lower yield and reliability. This problem is especially noticeable with various monitor patterns, or the like, built in one on the same chip, together with memory cells. This is problematic these patterns are indispensable to unify the quality of the semiconductor memory device and improve the yield.